|
Verilog Simulation Bridges the Gap Between PLDs and ASICs
|
8/99
|
|
Complex Designs
Demand Greater Attention to Data Management
|
8/99
|
|
Emerging Trends in PLD Tools
|
8/99
|
|
Viewpoint: A Roadmap to Evolving SOC Capability
|
8/99
|
|
The Compute
Ranch Takes Over EDA
|
8/99
|
|
Focus Report: Third Party Design Services
|
8/99
|
|
Viewpoint: Don't Forget the Software
|
7/99
|
|
Tools: Putting Pspice to the Test
|
7/99
|
|
Editorial: What Does Design Reuse Take?
|
7/99
|
|
EDA Platform Benchmark: Place and Route
|
7/99
|
|
Tell Me Again--What Does the "S" in SOC
Stand For?
|
7/99
|
|
Hardware-Software Codesign of an Image Processing Unit
|
7/99
|
|
Making the ASIC/FPGA Decision
|
7/99
|
|
Inside VHDL: Developing VITAL-Compliant VHDL
Models
|
7/99
|
|
Understanding Encroaching Parasitics Can Help to Ensure Signal Quality
|
6/99
|
|
Viewpoint: System Design Goes Beyond SOCs
|
6/99
|
|
Editorial" What's a Reasonable Price for EDA Tools?
|
6/99
|
|
New Orleans the Technical Way
|
6/99
|
|
EDA Standards for the Millennium
|
6/99
|
|
Static Timing
Analysis Increases ASIC Performance
|
6/99
|
|
Tackling the System Verification of a Network Router
|
6/99
|
|
Focus Report: HDL Add-in Tools
|
6/99
|
|
PLDs and
Their Users Benefit from In-Field Reconfiguration Options
|
5/99
|
|
Viewpoint: Verification--Just How Much Is Enough?
|
5/99
|
|
Dreaming Up a New Methodology for Physical Migration of Hard IP
|
5/99
|
|
Focus Report: Design Libraries
|
5/99
|
|
Modeling Substrate Effects in RF Integration
|
5/99
|
|
Automating Functional Design Verification
|
4/99
|
|
Using Clock Skew as a Tool to Achieve Optimal Timing
|
4/99
|
|
Taking a Graphical Approach to Programmable Logic Design
|
4/99
|
|
EDA Takes Advantage of an NT Compute Farm
|
4/99
|
|
Viewpoint: Take the High(-Level) Road to Fast Verification of Complex ASICs
|
4/99
|
|
Editorial: Got VSDM? Cooperate!
|
4/99
|
|
Truth Table Models for EDA Tools
|
4/99
|
|
Editorial: Spring Changes
|
3/99
|
|
Design Methodologies for DSM ASIC designs
|
3/99
|
|
Viewpoint: It's the Methodology, Not the Design Tools
|
3/99
|
|
EDA Platform: A Strategy for Linux EDA Success
|
3/99
|
|
Integrated System Design Environment Lowers Development Risk
|
3/99
|
|
Interconnect Verification Forms the Linchpin of a DSL VDSM Design
|
3/99
|
|
Focus Report: Formal Verification
|
2/99
|
|
Viewpoint: The Time Has Come for Knowledge based Debugging
|
2/99
|
|
Editoral: Making Better Use of the World Wide Web
|
2/99
|
|
Putting a RAID Controller Into a System-level FPGA
|
2/99
|
|
ASIC Issues: Accommodating Analog and Mixed-Signal Blocks in a System on a Chip
|
2/99
|
|
A PC-based Design Flow for Advanced Imaging ICs
|
2/99
|
|
Integrating Design and Test using New Tools and Techniques
|
2/99
|
|
Editorial: Struggling toward a New Methodology for Deep-Submicron Design
|
1/99
|
|
System Verification from the Ground Up
|
1/99
|
|
Special Section: EDA Platform Benchmark: Simulation and Synthesis II
|
1/99
|
|
Programmable Device or Gate Array?
|
1/99
|
|
Packaging Design for High-Performance ICs
|
1/99
|
|
Focus Report: Analog and Mixed-Signal Simulators
|
1/99
|
|
Viewpoint: The True Value of Virtual Test Software
|
12/98
|
|
Editorial: Free the PC!
|
12/98
|
|
Focus Report: Programmable Logic
|
12/98
|
|
A Virtual Test Revolution
|
12/98
|
|
Streamlining HDL Code Coverage Analysis
|
12/98
|
|
Codesigning a Complex System on a Chip with Behavioral Models
|
11/98
|
|
Physical Verification: Challenges and Problems for New Designs
|
11/98
|
|
EDA Platform Benchmark: Simulation and Synthesis at the Same Time
|
11/98
|
|
Editorial: Coming to Grips with Using Reusable IP
|
11/98
|
|
Test: The Final Hurdle for Systems on a Chip
|
10/98
|
|
Coding for the Future: How to Write Reusable VHDL
|
10/98
|
|
Editorial: Man vs. Machine: The IC Designer's Dilemma
|
10/98
|
|
Focus Report:
Windows EDA Tools
|
10/98
|
|
Editorial: Who's Got the Power?
|
9/98
|
|
Benchmark Feedback
|
9/98
|
|
Linux Has What It Takes for EDA
|
9/98
|
|
Toolbox: Test-Driving the Newest Version of Modelsim PE/Plus
|
9/98
|
|
Coverification Tames Cache and Bus Interface Controller Design
|
9/98
|
|
EDA Platform Benchmark:
Simulation II
|
9/98
|
|
Focus Report: Timing and Power Analysis
|
8/98
|
|
Editorial: Linux Wins the Shootout with Windows NT
|
8/98
|
|
Who Will Lead the
Development of the System-on-a-Chip Industry?
|
8/98
|
|
Multimedia Processor Design Presents Synthesis Challenges
|
8/98
|
|
Viewpoint: The New 'ASIC Replacement' FPGAs
|
8/98
|
|
Building Robust, Reliable Nanometer ICs
|
8/98
|
|
EDA Platform: What Really Happened at DAC?
|
8/98
|
|
Linux vs. Windows NT: Engineers Speak Out, Part 2
|
8/98
|
|
EDA Platform Benchmark: Synthesis
|
7/98
|
|
Practical Approaches to Improving ASIC Verification Efficiency
|
7/98
|
|
EDA Platform: An Industry at the Crossroads
|
7/98
|
|
The New System-Level Design Language
|
7/98
|
|
Engineers Speak Out: Linux vs. Windows NT, Part 1
|
7/98
|
|
Focus Report: Programmable Logic Design Tools
|
7/98
|
|
DAC Technical Sessions Speak to Designers' Issues
|
6/98
|
|
ASIC Issues: Matching the Design Size to an ASIC or FPGA
|
6/98
|
|
Addressing the Effects of Signal Integrity in Deep-Submicron Design
|
6/98
|
|
HDL Verification Coverage
|
6/98
|
|
Delivering IP: A Three-Pronged Attack
|
6/98
|
|
Newbridge Networks Adopts a Top-Down Verification Strategy
|
6/98
|
|
Focus Report: HDL Simulators
|
6/98
|
|
Viewpoint: The System IC Virtual Prototype: Virtually Certain to Be an Industry Milestone
|
5/98
|
|
Feedback: EDA
Platform
|
5/98
|
|
Verifying a Scalable Fault-Tolerant Interconnect under Windows NT
|
5/98
|
|
Graphical HDL Tools Promote Accuracy through Better Communication
|
5/98
|
|
At the Heart of a Mixed-Signal SOC Design: Mulitple Simulators
|
5/98
|
|
Implementing a DSP in Programmable Logic
|
5/98
|
|
Editorial: An Open Letter to the EDA Industry, or Tilting at Windmills
|
5/98
|
|
The New RTL Analysis Methodology
|
4/98
|
|
IP Design Flow Centers on Automatic HDL Translation
|
4/98
|
|
Focus Report: Electronic System-Level Design Tools
|
4/98
|
|
Automating the Design Flow from System to Gates
|
4/98
|
|
Hardware Emulation Accelerates HDL Functional Verification
|
4/98
|
|
Viewpoint: Code Coverage: 'Go with the Flow'
|
4/98
|
|
Real-Time Prototyping Settles the Design of a Mobile Handset
|
3/98
|
|
ESL Design Entry Delivers a Chip Primed for Reuse
|
3/98
|
|
The Art of
Embedding SRAM
|
3/98
|
|
Viewpoint: Cost or Performance--ASICs Still Beat FPGAs
|
3/98
|
|
EDA Platform Benchmark
|
3/98
|
|
Clock Tree Generator
Meets the Needs of High-Speed Deep-Submicron Designs
|
3/98
|
|
Designers Tackle the Testability of a System-Level IC
|
2/98
|
|
Design Methodology for Quickly and Accurately Generating SRAMs
|
2/98
|
|
Focus Report: High-Speed ASIC Benchmark
|
2/98
|
|
Viewpoint: Hot Carrier Effect--A Fading Concern or a Growing Problem?
|
2/98
|
|
Evaluating ASIC Memory Trade-offs
|
2/98
|
|
Developing Photo Opportunities of the Digital Sort
|
1/98
|
|
Viewpoint: Could EDA Roadblocks Derail Moore's Law?
|
1/98
|
|
CAMs Enhance Network Performance
|
1/98
|
|
Focus Report: Third-Party Design Services
|
1/98
|
|
DSM Needs a Rich Infrastructure
|
1/98
|
|
Concurrent Engineering Delivers at the Chip and System Level
|
12/97
|
|
Designers Gain When IP Vendors and Pure-Play Foundries Team Up
|
12/97
|
|
Readers Speak Out on DSM: Part 2
|
12/97
|
|
Editorial: Discovering a Reluctant New EDA Tool
Vendor
|
12/97
|
|
Deep-Submicron Designs Require Netlist Reduction for Fast Simulation
|
11/97
|
|
Property Verification Using Theorem Proving and Model Checking
|
11/97
|
|
Viewpoint: For Soft Cores, You Need More than Synthesizable HDL Code
|
11/97
|
|
Readers Speak Out on Deep Submicron
|
11/97
|
|
ASIC Issues: DSM Increases the Need for Experienced Design Teams
|
10/97
|
|
Programmable Notes: The Big Question in Counting FPGA Gates: Should Memory Be Included?
|
10/97
|
|
Years of Strong Growth Lie Ahead for High-Density Programmable Devices
|
10/97
|
|
Verifying a Million-Gate Processor
|
10/97
|
|
Viewpoint: The EDA Market Reformation: Not If but When
|
10/97
|
|
Focus Report:Windows for EDA Tools
|
10/97
|
|
Editorial: It's Time for the Return of the Silicon Compiler
|
9/97
|
|
Turning to Formal Verification
|
9/97
|
|
Managing Power in a Million-Gate IC Design
|
9/97
|
|
Deep-submicron processes require new design approaches and new design tools.
|
9/97
|
|
EDA Platform: What Really Happened at DAC
|
9/97
|
|
Building a Multimedia Video Conferencing Chip with a Synthesizable PCI Core
|
9/97
|
|
Viewpoint: Applying the Law of the Harvest to Electronic Product Development
|
9/97
|
|
Focus Report: Design Libraries
|
8/97
|
|
Viewpoint: Reconfigurable System Prototyping: A Fast Solution for
Functional Verification
|
8/97
|
|
The Seven Deadly Sins of Scan-Based Designs
|
8/97
|
|
Using Hierarchical Clock Tree Synthesis to Generate Balanced Clock Trees
|
8/97
|
|
Creating a Cost-Effective Alternate Supply for Single-Sourced ICs
|
8/97
|
|
ASIC Design Flow Scores on First Pass
|
8/97
|
|
Editorial: Spending the Evening with "ALF"
|
8/97
|
|
Viewpoint: Breaking the Interconnect Barrier
|
7/97
|
|
Top-Down Timing Design
|
7/97
|
|
3-D Parasitic Extraction for Deep Submicron IC Design
|
7/97
|
|
Solutions for H/W S/W Co-Design
|
7/97
|
|
Statistical Model Dispels Seven Myths of Graphics Designers
|
6/97
|
|
Concurrency Verification Is the Key to ASIC Design
|
6/97
|
|
HAL's 64-bit Architecture Helps EDA Vendors
|
6/97
|
|
Which Sessions Should You Attend at DAC?
|
6/97
|
|
Programmable Notes: Density Increases Spur a User Rush Toward Efficiencies of ISP
|
6/97
|
|
Transitioning from ABEL-HDL to VHDL
|
6/97
|
|
Logic Synthesis for the Next Generation
|
6/97
|
|
ASIC Multidimensional Design for Test
|
6/97
|
|
Developing an EDA Vendor-Independent ASIC Design System forVHDL
|
6/97
|
|
Mixed-Signal Modeling for ICs
|
6/97
|
|
A New Metric for Determining Design-Vector Completeness
|
5/97
|
|
Viewpoint: Do You Speak HDL?
|
5/97
|
|
ASIC Issues: Modeling Devices for Performance
|
5/97
|
|
Managing Power in Million-Device IC Design
|
5/97
|
|
Editorial: Finding Bugs Before They Become Bugs in Million-Gate Designs
|
5/97
|
|
FPGA Design Practices That Help Ensure Good Migration
|
5/97
|
|
A Case Study in Interface Verification
|
5/97
|
|
Effective Design Verification
|
4/97
|
|
Focus Report: HDL Add-In Tools
|
4/97
|
|
Viewpoint: The Next Frontier: High-Level Functional Verification
|
4/97
|
|
Editorial: Design-Tool Evolution About to Enter a New Cycle
|
4/97
|
|
FPGAs Shrink With Physical Design Reuse
|
4/97
|
|
Simulation Mixed-Signal Tests to Reduce Time-to-Market
|
4/97
|
|
Viewpoint: A Picture Is Worth a Thousand Megabytes
|
3/97
|
|
Low-Power ASIC Design
|
3/97
|
|
Designing the Ultimate Network Computer Board
|
3/97
|
|
Verifying the PA-8000's FPU
|
3/97
|
|
Editorial:Verilog Evolves to Meet Designer's Needs
|
3/97
|
|
Editorial: Trends In Deep Submicron Design Tools
|
2/97
|
|
Timing Analysis for the PA-8000
|
2/97
|
|
FPGA Design: Early Implications In Partitioning
|
2/97
|
|
Viewpoint: Language Fusion
|
1/97
|
|
Code Coverage Analysis Works In Hardware Design
|
1/97
|
|
FPGAs and Drop-in Modules
|
1/97
|
|
Tool Time for Processor Design
|
1/97
|
|
Special Section: CHDS--Next Paradigm for Deep Submicron EDA?
|
12/96
|
|
EDA Platform: IP in HDL Using EDA for IC
|
12/96
|
|
SPY vs. SPY: the VMC Story
|
12/96
|
|
Reconfigurable Logic Modeling
|
12/96
|
|
Editorial: Why I Believe You Should Vote "No" On California Propostion 211
|
12/96
|
|
A Set of Formal Applications
|
11/96
|
|
Focus Report: Third-Party Design and Consulting Services
|
11/96
|
|
Placement and Routing in Analog Design
|
11/96
|
|
ASIC Library Performance
|
11/96
|
|
Viewpoint: An Open Letter to the Electronics Industry
|
10/96
|
|
Electronic Component Information Exhchange
|
10/96
|
|
Reconstruction, Maintenance, and
Archival of FPGAs
|
10/96
|
|
Focus Report: Cores and Megacells
|
10/96
|
|
EDA Platform: A New HDL Environment
|
10/96
|
|
Memory Hierarchies & the Speed Gap
|
10/96
|
|
Viewpoint: Future Directions for the Verilog Language
|
9/96
|
|
Optimizing Layout on High-Speed Digital Printed Circuit Boards
|
9/96
|
|
Programmable Notes: Shrink-Wrap PLD Design Tools?
|
9/96
|
|
Implementing PCI in an FPGA
|
9/96
|
|
Automating MOTIVE
|
9/96
|
|
Reliability Management for
Deep Submicron ICs
|
9/96
|
|
Designing an ATM Chip
|
8/96
|
|
Partitioning System Designs
|
8/96
|
|
Fab and Silicon Performance
|
8/96
|
|
Focus Report: HDL Simulation Tools
|
8/96
|
|
Focus Report: Signal Integrity Tools
|
7/96
|
|
Cadence: the Good, the Bad, & the Ugly
|
7/96
|
|
Viewpoint: IC Power: a Hot Problem?
|
7/96
|
|
Delay Calculation Standard and Deep Submicron Design
|
7/96
|
|
Designing the UltraSPARC-1
|
6/96
|
|
Designing a 100-kgate Set-Top Box ASIC Using Behavioral Compiler with Verilog
|
6/96
|
|
Editorial: Overcoming Obstacles in Designing with Reusable Cores
|
6/96
|
|
Focus Report: Formal
Verification, Cycle-Based Simulation, Timing Analysis, and ESL Entry
|
6/96
|
|
Signal Reflection and Pedestal Effect of a Heavily Loaded Net
|
5/96
|
|
Functional Verification of Graphics Designs
|
5/96
|
|
Viewpoint: Why Windows NT for EDA?
|
5/96
|
|
Virtual Prototype Finds Design Flaws
|
5/96
|
|
Focus Report: Windows EDA Tools
|
4/96
|
|
The Great ESDA Shootout
|
4/96
|
|
Full Mixed-Signal Simulation Can Dramatically Improve a Design Process
|
4/96
|
|
Viewpoint: Faster CPUs are Only Part of the Solution for High-End EDA Applications
|
3/96
|
|
FPGA Flexibility Enables Concurrent Board Design and Layout
|
3/96
|
|
ASIC Issues: More Clocks in Less Time
|
3/96
|
|
An Evolution in System Design and Verification
|
3/96
|
|
A 1GB/s Graphics Controller
|
3/96
|
|
Focus Report: Analog and Mixed-Signal Simulation Tools
|
2/96
|
|
Viewpoint: The Era of the Mini-Methodology
|
2/96
|
|
Putting Multi-Threaded Behavioral Simulation to Work
|
2/96
|
|
Special Section: Design SuperCon '96: Coping with Increasing IC Complexity
|
2/96
|
|
Low-Power Key to
Implement 8-mm Tape Drive
|
2/96
|
|
Editorial: Time to Change the Metric for Measuring IC Feature Sizes
|
2/96
|
|
Designing an ATM SAR Controller
|
2/96
|
|
Design Reuse Enhances Productivity
|
2/96
|
|
Viewpoint: Defacto Standards Set the Pace--A Life-Cycle
|
1/96
|
|
Top-Down FPGA Design-A 12-Step Program
|
1/96
|
|
Designing a Highly Integrated Controller for Flash Storage Cards
|
1/96
|
|
Editorial: The Return of Hardware Prototypes Provides Peace of Mind
|
1/96
|
|
Viewpoint: Bridging the Programmable Logic Design Gap
|
12/95
|
|
ASIC Ground Bounce Case Study
|
12/95
|
|
Designing an Efficient UNIX-Based CAD Environment
|
11/95
|
|
High Performance Embedded Systems
|
11/95
|
|
Viewpoint: The Revolution in Programmable Logic Device Design
|
11/95
|
|
The Evolution of Core + ASIC Methodology
|
11/95
|
|
Packaging: More Than a Die Holder
|
10/95
|
|
Comparing Two Verilog Fault Simulators
|
10/95
|
|
Comparing Verilog to VHDL Syntactically and Semantically
|
10/95
|
|
Submicron Designs
Require New Verification Methods
|
10/95
|
|
Caution: Wireless IC Design Ahead
|
9/95
|
|
Automating Full-Chip Logic Synthesis
|
9/95
|
|
Trends In Simulation and Synthesis
|
9/95
|
|
Viewpoint: Defining "Shrink-Wrapped" for Windows/EDA
|
9/95
|
|
Optimizing Fault Detection for Boundary Scan Testing
|
9/95
|
|
Rorschach Testing 273 Engineers with the
Verilog/VHDL Contest
|
9/95
|
|
An Introduction to Parameterized Design With VHDL
|
8/95
|
|
Focus Report: Analog and Mixed-Signal Cells
|
8/95
|
|
Analog Language
Standards Need Working Models
|
8/95
|
|
Verilog Won and VHDL Lost? You Be the Judge
|
7/95
|
|
Co-Verification Strategies In Hardware-Software Co-Design
|
7/95
|
